Low Power Dynamic CMOS Full-Adder Cell
نویسندگان
چکیده
In this paper a new area efficient, high-speed and ultra-low power 1-bit full adder cell is presented. The performance: power, time delay and power delay product (PDP) of the proposed adder cell has been analyzed in comparison with the four existent low-power, high-speed adders. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology and intensive simulation runs on Cadence environment shows that the new full adder has more than 16% in power savings over C-CMOS full adder. Keywords— Low-Power, Full-Adder, CMOS.
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